1. Field of the Invention
The present invention relates generally to semiconductor structures and manufacturing. More particularly, the present invention relates to the formation of metal-insulator-metal capacitors.
2. Related Art
Advances in semiconductor manufacturing technology have led to the integration of millions of circuit elements, such as transistors, on a single integrated circuit (IC). In order to integrate increasing numbers of circuit elements onto an IC it has been necessary to reduce the dimensions of the various component parts. Not only have interconnect line widths become smaller, but so have the dimensions of metal-oxide-semiconductor field effect transistors and other integrated devices, such as capacitors.
Metal-electrode capacitors are widely used in mixed-signal/radio frequency (RF) ICs for better linearity and higher Q (quality factor) (due to lower electrode resistance). MIM (metal-insulator-metal) capacitors have been commercially available in the standard CMOS (complimentary metal oxide silicon) mixed-signal process with aluminum interconnect, by adding steps to the process flow. However, similar MIM capacitors are being developed for the most advanced copper interconnects, which is replacing the aluminum interconnects in the 0.15 μm (micrometer=10−6) generation and beyond. Due to the uniqueness in the copper damascene process, there is no simple/low-cost way of making MIM capacitors.
What is desired is a method of making copper MIM capacitors using fully compatible CMOS logic process techniques.